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1.5 on resistance, 15 v/12 v/5 v, 4:1, i cmos multiplexer adg1404 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2009 analog devices, inc. all rights reserved. features 1.5 on resistance 0.3 on-resistance flatness 0.1 on-resistance match between channels up to 400 ma continuous current fully specified at +12 v, 15 v, and 5 v no v l supply required 3 v logic-compatible inputs rail-to-rail operation 14-lead tssop and 4 mm 4 mm, 16-lead lfcsp applications automatic test equipment data acquisition systems battery-powered systems sample-and-hold systems audio signal routing communication systems relay replacement functional block diagram s1 s2 d s3 s4 a0 a1 en 1 of 4 decoder adg1404 06816-001 figure 1. general description the adg1404 is a complementary metal-oxide semiconductor (cmos) analog multiplexer, comprising four single channels designed on an i cmos? process. i cmos (industrial cmos) is a modular manufacturing process that combines high voltage cmos and bipolar technologies. it enables the development of a wide range of high performance analog ics capable of 33 v operation in a footprint that no previous generation of high voltage parts has been able to achieve. unlike analog ics using conventional cmos processes, i cmos components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. the on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. i cmos construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery- powered instruments. the adg1404 switches one of four inputs to a common output, d, as determined by the 3-bit binary address lines, a0, a1, and en. logic 0 on the en pin disables the device. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condi- tion, signal levels up to the supplies are blocked. all switches exhibit break-before-make switching action. inherent in the design is low charge injection for minimum transients when switching the digital inputs. product highlights 1. 2.6 maximum on resistance over temperature. 2. minimum distortion. 3. ultralow power dissipation: <0.03 w. 4. 14-lead tssop and 16-lead, 4 mm 4 mm lfcsp package.
adg1404 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? 15 v dual supply .......................................................................... 3 ? 12 v single supply ........................................................................ 4 ? 5 v dual supply ............................................................................ 5 ? continuous current, s or d .........................................................6 ? absolute maximum ratings ............................................................7 ? esd caution...................................................................................7 ? pin configurations and function descriptions ............................8 ? truth table .....................................................................................8 ? typical performance characteristics ..............................................9 ? terminology .................................................................................... 12 ? test circuits ..................................................................................... 13 ? outline dimensions ....................................................................... 16 ? ordering guide .......................................................................... 16 ? revision history 3/09rev. 0 to rev. a changes to power requirements, i dd , digital inputs = 5 v parameter, table 1 ............................................................................. 3 changes to power requirements, i dd , digital inputs = 5 v parameter, table 2 ............................................................................. 4 updated outline dimensions ....................................................... 16 7/08revision 0: initial version
adg1404 rev. a | page 3 of 16 specifications 15 v dual supply v dd = 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance (r on ) 1.5 typ v s = 10 v, i s = ?10 ma; see figure 22 1.8 2.3 2.6 max v dd = +13.5 v, v ss = ?13.5 v on-resistance match between channels (r on ) 0.1 typ v s = 10 v, i s = ?10 ma 0.18 0.19 0.21 max on-resistance flatness (r flat(on) ) 0.3 typ v s = 10 v, i s = ?10 ma 0.36 0.4 0.45 max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off) 0.03 na typ v s = 10 v, v s = ? 10 v; see figure 23 0.55 2 12.5 na max drain off leakage, i d (off) 0.04 na typ v s = 10 v, v s = ? 10 v; see figure 23 0.55 4 30 na max channel on leakage, i d , i s (on) 0.1 na typ v s = v d = 10 v; see figure 24 2 4 30 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i nh 0.005 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3.5 pf typ dynamic characteristics 1 transition time, t transition 150 ns typ r l = 300 , c l = 35 pf 180 220 250 ns max v s = +10 v; see figure 29 t on (en) 100 ns typ r l = 300 , c l = 35 pf 120 145 165 ns max v s = +10 v; see figure 31 t off (en) 110 ns typ r l = 300 , c l = 35 pf 135 165 185 ns max v s = +10 v; see figure 31 break-before-make time delay, t bbm 35 ns typ r l = 300 , c l = 35 pf 10 ns min v s1 = v s2 = 10 v; see figure 30 charge injection ?20 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 32 off isolation 70 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 25 channel-to-channel crosstalk 82 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 27 total harmonic distortion + noise 0.011 % typ r l = 110 , 10 v p-p, f = 20 hz to 20 khz; see figure 28 ?3 db bandwidth 55 mhz typ r l = 50 , c l = 5 pf; see figure 26 insertion loss ?0.17 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 c s (off) 23 pf typ f = 1 mhz, v s = 0 v c d (off) 90 pf typ f = 1 mhz, v s = 0 v c d , c s (on) 170 pf typ f = 1 mhz, v s = 0 v power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1 a max i dd 170 a typ digital inputs = 5 v 285 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 4.5/16.5 v min/max gnd = 0 v 1 guaranteed by design, not subject to production test.
adg1404 rev. a | page 4 of 16 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 2.8 typ v s = 0 v to 10 v, i s = ?10 ma; see figure 22 3.5 4.3 4.8 max v dd = 10.8 v, v ss = 0 v on-resistance match between channels (r on ) 0.13 typ v s = 0 v to 10 v, i s = ?10 ma 0.21 0.23 0.25 max on-resistance flatness (r flat(on) ) 0.6 typ v s = 0v to 10 v, i s = ?10 ma 1.1 1.2 1.3 max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 23 0.55 2 12.5 na max drain off leakage, i d (off) 0.03 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 23 0.55 4 30 na max channel on leakage, i d , i s (on) 0.1 na typ v s = v d = 1 v or 10 v; see figure 24 1.5 4 30 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3.5 pf typ dynamic characteristics 1 transition time, t transition 230 ns typ r l = 300 , c l = 35 pf 300 375 430 ns max v s = 8 v; see figure 29 t on (en) 180 ns typ r l = 300 , c l = 35 pf 240 295 335 ns max v s = 8 v; see figure 31 t off (en) 115 ns typ r l = 300 , c l = 35 pf 160 190 220 ns max v s = 8 v; see figure 31 break-before-make time delay, t bbm 100 ns typ r l = 300 , c l = 35 pf 10 ns min v s1 = v s2 = 8 v; see figure 30 charge injection 30 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 32 off isolation 80 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 25 channel-to-channel crosstalk 82 db typ r l = 50 , c l = 5 pf, f = 100 k hz; see figure 27 ?3 db bandwidth 35 mhz typ r l = 50 , c l = 5 pf; see figure 26 insertion loss ?0.3 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 c s (off) 39 pf typ f = 1 mhz, v s = 6 v c d (off) 150 pf typ f = 1 mhz, v s = 6 v c d , c s (on) 217 pf typ f = 1 mhz, v s = 6 v power requirements v dd = 13.2 v i dd 0.001 a typ digital inputs = 0 v or v dd 1 a max i dd 170 a typ digital inputs = 5 v 285 a max v dd 5/16.5 v min/max gnd = 0 v, v ss = 0 v 1 guaranteed by design, not subject to production test.
adg1404 rev. a | page 5 of 16 5 v dual supply v dd = 5 v 10%, v ss = ?5 v 10%, gnd = 0 v, unless otherwise noted. table 3. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance (r on ) 3.3 typ v s = 4.5 v, i s = ?10 ma; see figure 22 4 4.9 5.4 max v dd = +4.5 v, v ss = ?4.5 v on-resistance match between channels (?r on ) 0.13 typ v s = 4.5 v, i s = ?10 ma 0.22 0.23 0.25 max on-resistance flatness (r flat(on) ) 0.9 typ v s = 4.5 v, i s = ?10 ma 1.1 1.24 1.31 max leakage currents v dd = +5.5 v, v ss = ?5.5 v source off leakage, i s (off) 0.02 na typ v s = 4.5 v, v d = ? 4.5 v; see figure 23 0.2 1 12.5 na max drain off leakage, i d (off) 0.02 na typ v s = 4.5 v, v d = ? 4.5 v; see figure 23 0.25 1.2 15 na max channel on leakage, i d , i s (on) 0.05 na typ v s = v d = 4.5 v; see figure 24 0.25 1.5 20 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 5 pf typ dynamic characteristics 1 transition time, t transition 340 ns typ r l = 300 , c l = 35 pf 470 560 615 ns max v s = 3 v; figure 29 t on (en) 260 ns typ r l = 300 , c l = 35 pf 355 430 480 ns max v s = 3 v; figure 31 t off (en) 220 ns typ r l = 300 , c l = 35 pf 315 365 400 ns max v s = 3 v; figure 31 break-before-make time delay, t bbm 100 ns typ r l = 300 , c l = 35 pf 50 ns min v s1 = v s2 = 3 v; see figure 30 charge injection 30 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 32 off isolation 80 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 25 channel-to-channel crosstalk 82 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 27 ?3 db bandwidth 40 mhz typ r l = 50 , c l = 5 pf; see figure 26 insertion loss 0.27 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 total harmonic distortion + noise 0.03 % typ r l = 110 , 2.5 v p-p, f = 20 hz to 20 khz; see figure 28 c s (off) 33 pf typ v s = 0 v, f = 1 mhz c d (off) 128 pf typ v s = 0 v, f = 1 mhz c d , c s (on) 210 pf typ v s = 0 v, f = 1 mhz power requirements v dd = 5.5 v, v ss = ?5.5 v i dd 0.001 a typ digital inputs = 0 v, 5 v, or v dd 1 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 4.5/16.5 v min/max gnd = 0 v 1 guaranteed by design, not subject to production test.
adg1404 rev. a | page 6 of 16 continuous current, s or d table 4. parameter 25c 85c 125c unit test conditions/comments continuous current, s or d 1 15 v dual supply v dd = +13.5 v, v ss = ?13.5 v adg1404 tssop 350 220 100 ma max adg1404 lfcsp 450 300 140 ma max 12 v single supply v dd = 10.8 v, v ss = 0 v adg1404 tssop 300 220 100 ma max adg1404 lfcsp 400 300 140 ma max 5 v dual supply v dd = +4.5 v, v ss = ?4.5 v adg1404 tssop 300 220 100 ma max adg1404 lfcsp 400 300 140 ma max 1 guaranteed by design, not subject to production test.
adg1404 rev. a | page 7 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs gnd ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d 600 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, s or d 2 data + 15% operating temperature range automotive (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 14-lead tssop, ja thermal impedance (4-layer board) 112c/w 16-lead lfcsp, ja thermal impedance 30.4c/w reflow soldering peak temperature, pb free 260(+0/?5)c 1 overvoltages at in, s, and d are clamped by internal diodes. current should be limited to the maximum ratings given. 2 see data given in table 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. esd caution
adg1404 rev. a | page 8 of 16 pin configurations and function descriptions adg1404 nc = no connect 1 2 3 4 5 6 7 en v ss s1 nc d s2 a0 14 13 12 11 10 9 8 gnd v dd s3 nc nc s4 a1 top view (not to scale) 06816-002 figure 2. tssop pin configuration notes 1. exposed pad tied to substrate, v ss . 2. nc = no connect. pin 1 indicator 1v ss 2 nc 3 s1 4 s2 11 v dd 12 gnd 10 s3 9s4 5 nc 6 d 7 nc 8 nc 15 a 0 16 en 14 a1 13 nc top view (not to scale) adg1404 0 6816-003 figure 3. lfcsp pin configuration table 6. pin function descriptions pin no. tssop lfcsp mnemonic description 1 15 a0 logic control input. 2 16 en active high digital input. when this pin is low, the device is disabled and all switches are off. when this pin is high, the ax logi c inputs determine the on switches. 3 1 v ss most negative power supply potential. 4 3 s1 source terminal. can be an input or an output. 5 4 s2 source terminal. can be an input or an output. 6 6 d drain terminal. can be an input or an output. 7 to 9 2, 5, 7, 8, 13 nc no connection. 10 9 s4 source terminal. can be an input or an output. 11 10 s3 source terminal. can be an input or an output. 12 11 v dd most positive power supply potential. 13 12 gnd ground (0 v) reference. 14 14 a1 logic control input. truth table table 7. en a1 a0 s1 s2 s3 s4 0 x x off off off off 1 0 0 on off off off 1 0 1 off on off off 1 1 0 off off on off 1 1 1 off off off on
adg1404 rev. a | page 9 of 16 typical performance characteristics 2.5 2.0 1.5 1.0 0.5 0 ?16.5 ?12.5 ?8.5 ?4.5 ?0.5 3.5 7.5 15.5 on resistance ( ? ) v s or v d (v) 11.5 v dd = +16.5v, v ss = ?16.5v t a = 25c i s = ?10ma v dd = +15v, v ss = ?15v v dd = +13.5v, v ss = ?13.5v v dd = +12v, v ss = ?12v v dd = +10v, v ss = ?10v 06816-004 figure 4. on resistance as a function of v d (v s ), dual supply 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?7 ?6 ?5 ?3 ?1 ?4 ?2 0 1 6 on resistance ( ? ) v s or v d (v) 34 7 5 2 t a = 25c i s = ?10ma v dd = +7v, v ss = ?7v v dd = +5.5v, v ss = ?5.5v v dd = +5v, v ss = ?5v v dd = +4.5v, v ss = ?4.5v 06816-005 figure 5. on resistance as a function of v d (v s ), dual supply 7 6 5 4 3 2 1 0 014 12 10 8642 on resistance ( ? ) v s or v d (v) t a = 25c i s = ?10ma v dd = 15v, v ss = 0v v dd = 13.2v, v ss = 0v v dd = 12v, v ss = 0v v dd = 10.8v, v ss = 0v v dd = 8v, v ss = 0v v dd = 5v, v ss = 0v 06816-006 figure 6. on resistance as a function of v d (v s ), single supply 3.0 2.5 2.0 1.5 1.0 0.5 0 ?15 15 10 5 0 ?5 ?10 on resistance ( ? ) v s or v d (v) v dd = +15v v ss = ?15v i s = ?10ma t a = +25c t a = +85c t a = +125c t a = ?40c 06816-007 figure 7. on resistance as a function of v d (v s ) for different temperatures, 15 v dual supply 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 on resistance ( ? ) v s or v d (v) v dd = +5v v ss = ?5v i s = ?10ma t a = +25c t a = +85c t a = +125c t a = ?40c 06815-108 figure 8. on resistance as a function of v d (v s ) for different temperatures, 5 v dual supply 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 012 10 8 6 4 2 on resistance ( ? ) v s or v d (v) v dd = 12v v ss = 0v i s = ?10ma t a = +25c t a = +85c t a = +125c t a = ?40c 06815-109 figure 9. on resistance as a function of v d (v s ) for different temperatures, single supply
adg1404 rev. a | page 10 of 16 6 4 2 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 0 20406080100120 leakage (na) temperature (c) 06816-111 v dd = +15v v ss = ?15v v bias = +10v/?10v i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i d , i s (on) + + i d , i s (on) ? ? figure 10. leakage currents as a function of temperature,15 v dual supply 4 ?4 ?3 ?2 ?1 0 1 2 3 0 20406080100120 leakage (na) temperature (c) 06816-112 v dd = +5v v ss = ?5v v bias = +4.5v/?4.5v i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i d , i s (on) + + i d , i s (on) ? ? figure 11. leakage currents as a function of temperature, 5 v dual supply 14 ?4 ?2 0 2 4 6 8 10 12 0 20406080100120 leakage (na) temperature (c) 06816-113 v dd = 12v v ss = 0v v bias = 1v/10v i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i d , i s (on) + + i d , i s (on) ? ? figure 12. leakage currents as a function of temperature, 12 v single supply 80 70 60 50 40 30 20 10 0 014 12 10 8642 i dd (a) logic, ax (v) t a = 25c i dd per logic input v dd = +15v v ss = ?15v v dd = +12v v ss = 0v v dd = +5v v ss = ?5v 06815-008 figure 13. i dd vs. logic level 600 400 200 0 ?200 ?400 ?600 ?15 ?10 ?5 0 5 10 15 charge injection (pc) v s (v) v dd = +15v, v ss = ?15v v dd = +12v, v ss = 0v v dd = +5v, v ss = ?5v t a = 25c 06816-012 figure 14. charge injection vs. source voltage 500 0 50 100 150 200 250 300 350 400 450 ?40 ?20 0 20 40 60 80 120 time (ns) temperature (c) 100 v dd = +15v, v ss = ?15v v dd = +12v, v ss = 0v v dd = +5v, v ss = ?5v 06816-013 figure 15. transition times vs. temperature
adg1404 rev. a | page 11 of 16 0 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 1k 10k 100k 1m 10m 100m off isolation (db) frequency (hz) t a = 25c 06816-014 figure 16. off isol ation vs. frequency 0 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 1k 10k 100k 1m 10m 100m crosstalk (db) frequency (hz) t a = 25c 06816-015 figure 17. crosstalk vs. frequency 0 ?7 ?6 ?5 ?4 ?3 ?2 ?1 1k 10k 100k 1m 10m 100m insertion loss (db) frequency (hz) v dd = +15v v ss = ?15v t a = 25c 06816-016 figure 18. on response vs. frequency 0.024 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.002 10 100 1k 10k 100k thd + n (%) frequency (hz) v dd = +15v v ss = ?15v t a = 25c v s = 20v p-p v s = 15v p-p 06816-017 v s = 10v p-p figure 19. thd + n vs. frequency at 15 v 1 0.1 0.01 0.001 10 100 1k 10k 100k thd + n (%) frequency (hz) v dd = +5v v ss = ?5v t a = 25c v s = 10v p-p v s = 5v p-p v s = 2.5v p-p 06816-018 figure 20. thd + n vs. frequency at 5 v 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 1k 10k 100k 1m 10m acpsrr (db) frequency (hz) v dd = +15v v ss = ?15v v p-p = 0.63v t a = 25c no decoupling capacitors decoupling capacitors on supplies 06815-017 figure 21. acpsrr vs. frequency
adg1404 rev. a | page 12 of 16 terminology i dd the positive supply current. i ss the negative supply current. v d (v s ) the analog voltage on terminal d and terminal s. r on the ohmic resistance between terminal d and terminal s. r flat(on) flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. i s (off) the source leakage current with the switch off. i d (off) the drain leakage current with the switch off. i d , i s (on) the channel leakage current with the switch on. v inl the maximum input voltage for logic 0. v inh the minimum input voltage for logic 1. i inl (i inh ) the input current of the digital input. c s (off) the off switch source capacitance, which is measured with reference to ground. c d (off) the off switch drain capacitance, which is measured with reference to ground. c d , c s (on) the on switch capacitance, which is measured with reference to ground. c in the digital input capacitance. t transition the delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another. t on (en) the delay between applying the digital control input and the output switching on. see figure 29, test circuit 4. t off (en) the delay between applying the digital control input and the output switching off. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. thd + n the ratio of the harmonic amplitude plus noise of the signal to the fundamental. acpsrr (ac power supply rejection ratio) the ratio of the amplitude of signal on the output to the amplitude of the modulation. this is a measure of the parts ability to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p-p.
adg1404 rev. a | page 13 of 16 test circuits i ds sx d v s v 06816-020 figure 22. on resistance sx d v s a a v d i s (off) i d (off) 06816-021 figure 23. off leakage sx d a v d i d (on) nc nc = no connect 06816-022 figure 24. on leakage v out 50 ? network analyzer r l 50? sx d v s v dd v ss 0.1f v dd 0.1f v ss gnd 50? off isolation = 20 log v out v s 0 6816-027 figure 25. off isolation v out 50? network analyzer r l 50? sx d v s v dd v ss 0.1f v dd 0.1f v ss gnd insertion loss = 20 log v out with switch v out without switch 06816-028 figure 26. bandwidth channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50 ? r l 50? v s v s v dd v ss 0.1f v dd 0.1f v ss 06816-029 figure 27. channel-to-channel crosstalk
adg1404 rev. a | page 14 of 16 v out r s audio precision r l 110? in v in sx d v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 06816-030 figure 28. thd + noise v in s1 d gnd c l 35pf r l 300? v out 50% 50% 90% 90% address drive (v in ) ) v out a0 a1 s4 s3 s2 v s1 v s4 en 2.4v 0v 3v t transition t transition v dd 0.1f v ss v dd v ss 0.1f 06816-023 figure 29. address to output switching times address drive (v in ) v out v in s1 d gnd c l 35pf r l 300? 300? v out a0 a1 s4 s3 s2 v s1 en 2.4v v dd 0.1f v ss v dd v ss 0.1f t bbm 80% 80% 0v 3v 06816-024 figure 30. break-before-make time delay
adg1404 rev. a | page 15 of 16 enable drive (v in ) s1 d gnd c l 35pf r l 300? v out a0 a1 s4 s3 s2 v s en v dd 0.1f v ss v dd v ss 0.1f v in 300? t off (en) t on (en) 50% 50% 0.9v out 0.9v out output 0v 3v v out 0v 06816-025 figure 31. enable-to-output switching delay sx d v s gnd r s sw off q inj = c l v out sw off sw on sw off sw off a2a1 en v dd v ss v dd decoder v ss v out v out v in v in v out c l 1nf 0 6816-026 figure 32. charge injection
adg1404 rev. a | page 16 of 16 outline dimensions compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 33. 14-lead thin shrink small outline package [tssop] (ru-14) dimension shown in millimeters compliant to jedec standards mo-220-vggc. 1 0.65 bsc 0.60 max p i n 1 i n d i c a t o r 1.95 bcs 0.50 0.40 0.30 0.25 min 3.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indi c ator coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 4.00 bsc sq 2.65 2.50 sq 2.35 16 5 13 8 9 12 4 exposed pad bottom view 031006-a figure 34. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-16-13) dimensions shown in millimeters ordering guide model temperature range packag e description package option adg1404yruz 1 ?40c to +125c 14-lead thin shrink small outline package (tssop) ru-14 ADG1404YRUZ-REEL7 1 ?40c to +125c 14-lead thin shrink small outline package (tssop) ru-14 adg1404ycpz-reel 1 ?40c to +125c 16-lead lead frame chip scale package (lfcsp_vq) cp-16-13 adg1404ycpz-reel7 1 ?40c to +125c 16-lead lead frame chip scale package (lfcsp_vq) cp-16-13 1 z = rohs compliant part. ?2008C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06841-0-3/09(a)

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